View X9110TV14_607162.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
X9110
Dual Supply/Low Power/1024-Tap/SPI Bus
Data Sheet October 7, 2005 FN8158.2
Single Digitally-Controlled (XDCPTM) Potentiometer
The X9110 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* 1024 Resistor Taps - 10-Bit Resolution * SPI Serial Interface for write, read, and transfer operations of the potentiometer * Wiper Resistance, 40 Typical @ 5V * Four Non-Volatile Data Registers * Non-Volatile Storage of Multiple Wiper Positions * Power-on Recall. Loads Saved Wiper Position on Power-up * Standby Current < 3A Max * System VCC: 2.7V to 5.5V Operation * Analog V+/V-: -5V to +5V * 100k End to End Resistance * 100 yr. Data Retention * Endurance: 100, 000 Data Changes Per Bit Per Register * 14 Ld TSSOP * Dual Supply Version of the X9111 * Low Power CMOS * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
X9110 14 LD TSSOP TOP VIEW
V+ S0 A0 SCK WP SI VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RL RH RW HOLD CS V-
Functional Diagram
VCC RH V+
ADDRESS DATA STATUS SPI BUS INTERFACE
BUS INTERFACE & CONTROL
WRITE READ TRANSFER
POWER-ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3) WIPER
100k 1024-TAPS POT
CONTROL
VSS
NC
NC
RW
RL
V-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas INC. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9110 Ordering Information
PART NUMBER X9110TV14 X9110TV14Z (Note) X9110TV14I X9110TV14IZ (Note) X9110TV14-2.7 X9110TV14Z-2.7 (Note) X9110TV14I-2.7 X9110TV14IZ-2.7 (Note) PART MARKING X9110TV X9110TV Z X9110TV I X9110TV Z I X9110TV F X9110TV Z F X9110TV G X9110TV Z G 2.7 to 5.5 VCC LIMITS (V) 5 10 POTENTIOMETER RANGE (k) 100 TEMP RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Detailed Functional Diagram
VCC V+
HOLD CS SCK SO SI A0 INTERFACE AND CONTROL CIRCUITRY
POWER ON RECALL DR0 DATA DR2 CONTROL DR3 DR1 WIPER COUNTER REGISTER (WCR) 100k 1024-TAPS RL RW RH
WP
VSS
V-
2
FN8158.2 October 7, 2005
X9110 Circuit Level Applications
* Vary the gain of a voltage amplifier * Provide programmable dc reference voltages for comparators and detectors * Control the volume in audio circuits * Trim out the offset voltage error in a voltage amplifier circuit * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits * Vary the frequency and duty cycle of timer ICs * Vary the dc biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits
Pin Descriptions
PIN (TSSOP) 11 12 13 14 SYMBOL RW RH RL VCC FUNCTION Wiper Terminal of the Potentiometer High Terminal of the Potentiometer Low Terminal of the Potentiometer System Supply Voltage
Bus Interface Pins
SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out on the falling edge of the serial clock. SERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9110. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A0) The address input is used to set the 8-bit slave address. A match in the slave address serial data stream A0 must be made with the address input (A0) in order to initiate communication with the X9110. CHIP SELECT (CS) When CS is HIGH, the X9110 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9110, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers.
System Level Applications
* Adjust the contrast in LCD displays * Control the power level of LED transmitters in communication systems * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Control the gain in audio and home entertainment systems * Provide the variable DC bias for tuners in RF wireless systems * Set the operating points in temperature control systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems
Pin Descriptions
PIN (TSSOP) 1 2 3 4 5 6 7 8 9 10 SYMBOL V+ SO A0 SCK WP SI VSS VCS HOLD FUNCTION Analog Supply Voltage Serial Data Output Device Address Serial Clock Hardware Write Protect Serial Data Input System Ground Analog Supply Voltage Chip Select Device Select. Pause the Serial Bus
3
FN8158.2 October 7, 2005
X9110
Serial Data Path From Interface Circuitry Register 0 (DR0) 10 Register 1 (DR1) 10
Serial Bus Input C O U N T E R D E C O D E
RH
Parallel Bus Input Wiper Counter Register (WCR)
Register 2 (DR2)
Register 3 (DR3)
If WCR = 000[HEX] then RW = RL If WCR = 3FF[HEX] then RW = RH RL
R W FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Potentiometer Pins
RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer.
on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. ARRAY DESCRIPTION The X9110 is comprised of a resistor array (Figure 1). The array contains the equivalent of 1023 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within the individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. WIPER COUNTER REGISTER (WCR) The X9110 contains a Wiper Counter Register (See Table 1) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The contents of the WCR can be altered in one of three ways: (1) it may be written directly by the host via the write Wiper Counter Register instruction (serial load); (2) it
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. ANALOG SUPPLY VOLTAGES (V+ AND V-) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer.
Principles Of Operation
Device Description
SERIAL INTERFACE The X9110 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked-in
4
FN8158.2 October 7, 2005
X9110
may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register; (3) it is loaded with the contents of its data register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9110 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. DATA REGISTERS (DR) The potentiometer has four 10-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. DR[9:0] is used to store one of the 1024 wiper position (0 ~1023). Table 2. STATUS REGISTER (SR) This 1-bit status register is used to store the system status (see Table 3). WIP: Write In Progress status bit, read only. * When WIP=1, indicates that high-voltage write cycle is in progress. * When WIP=0, indicates that no high-voltage write cycle is in progress.
TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9-WCR0: Used To Store The Current Wiper Position (Volatile, V) WCR9 V (MSB) TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9-BIT 0: Used to store wiper positions or data (Non-Volatile, NV) BIT 9 NV MSB TABLE 3. STATUS REGISTER, SR (1-BIT) WIP (LSB) BIT 8 NV BIT 7 NV BIT 6 NV BIT 5 NV BIT 4 NV BIT 3 NV BIT 2 NV BIT 1 NV BIT 0 NV LSB WCR8 V WCR7 V WCR6 V WCR5 V WCR4 V WCR3 V WCR2 V WCR1 V WCR0 V (LSB)
5
FN8158.2 October 7, 2005
X9110
TABLE 4. IDENTIFICATION BYTE FORMAT Device Type Identifier Internal Slave Address Read or Write Bit
ID3 0 (MSB)
ID2 1
ID1 0
ID0 1
0
0
A0
R/W (LSB)
TABLE 5. INSTRUCTION BYTE FORMAT Instruction Opcode Register Selection
I2 (MSB)
I1
I0
0
RB
RB 0 0 1 1 RA 0 1 0 1
RA
Register DR0 DR1 DR2 DR3
0
0 (LSB)
Device Instructions
Identification Byte (ID and A)
The first byte sent to the X9110 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device ID for the X9110; this is fixed as 0101[B] (refer to Table 4). The A0 bit in the ID byte is the internal slave address. The physical device address is defined by the state of the A0 input pin. The slave address is externally specified by the user. The X9110 compares the serial data stream with the address input state; a successful compare of the address bit is required for the X9110 to successfully continue the command sequence. Only the device whose slave address matches the incoming device address sent by the master executes the instruction. The A0 input can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit is used to set the device to either read or write mode.
Five of the seven instructions are four bytes in length. These instructions are: * Read Wiper Counter Register - read the current wiper position of the selected pot, * Write Wiper Counter Register - change current wiper position of the selected pot, * Read Data Register - read the contents of the selected data register; * Write Data Register - write a new value to the selected data register. * Read Status - This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. The Read Status Register instruction is the only unique format (see Figure 4). Two instructions require a two-byte sequence to complete (See Figure 2). These instructions transfer data between the host and the X9110; either between the host and one of the
Instruction Byte and Register Selection
The next byte sent to the X9110 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 5.
Data Registers or directly between the host and the Wiper Counter Register. These instructions are: * XFR Data Register to Wiper Counter Register - This transfers the contents of one specified Data Register to 6
the associated Wiper Counter Register. * XFR Wiper Counter Register to Data Register - This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register.
FN8158.2 October 7, 2005
X9110
See Instruction format for more details.
Power-up and Down Requirements
At all times, the V+ voltage must be greater than or equal to the voltage at RH or RL, and the voltage at RH or RL must be greater than or equal to the voltage at V-. During power-up and power-down, VCC, V+, and V- must reach their final values within 1msec of each other.
Write in Process (WIP bit)
The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command (See Figure 4).
CS
SCK
SI
0 ID3
1 ID2
0 ID1
1 ID0
0 0
0 0 A0 R/W I2 I1 I0
0 RB RA
0 0
0 0
Device ID
Internal Address
Instruction Opcode
Register Address
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0
1
0
1
00
0 A0 R/W I2 I1
0
X
X
0
0X
X
XX
XX W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0
ID3 ID2 ID1 ID0 0 Device ID
I0 0 RB RA 0 0 Register Address
Internal Address
Instruction Opcode
Wiper Position
FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
CS
SCK
SI
0
1
0
1
00
1 A0 R/W I2 I1 I0
0
X
X
0
0 0
X
XXX
XXXX
0
0
0
00
00 WIP Status Bit
ID3 ID2 ID1 ID0 0 0 Device ID
0 RB RA 0 Register Address
Internal Address
Instruction Opcode
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
7
FN8158.2 October 7, 2005
X9110
TABLE 6. INSTRUCTION SET INSTRUCTION SET INSTRUCTION Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Read Status (WIP bit) R/W 1 0 1 0 1 I2 1 1 1 1 1 I1 0 0 0 1 1 I0 0 1 1 0 0 0 0 0 0 0 0 RB 0 0 1/0 1/0 1/0 RA 0 0 1/0 1/0 1/0 0 0 0 0 0 0 0 0 0 0 0 0 OPERATION Read the contents of the Wiper Counter Register Write new value to the Wiper Counter Register Read the contents of the Data Register pointed to RB-RA Write new value to the Data Register pointed to RB-RA Transfer the contents of the Data Register pointed to by RB-RA to the Wiper Counter Register Transfer the contents of the Wiper Counter Register to the Data Register pointed to by RB-RA Read the status of the internal write cycle, by checking the WIP bit (read status register).
0
1
1
1
0
1/0
1/0
0
0
1
0
1
0
0
0
0
0
1
NOTE: 1/0 = data is one or zero
Instruction Format Read Wiper Counter Register (WCR)
Device Type Identifier CS Falling Edge Device Addresses R/ W = 1 Instruction Opcode Register Addresses Wiper Position (Sent by X9110 on SO) W C XXXXXXR 9 W C R 8 W C R 7 Wiper Position (sent by X9110 on SO) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS W Rising C Edge R 0
0
1
0
1
0
0 A0
1
0
0
0
0
0
0
0
Write Wiper Counter Register (WCR)
Device Type Identifier CS Falling Edge Device Addresses R/ W = 0 Instruction Opcode Register Addresses Wiper Position (Sent by Master on SI) W C XXXXXXR 9 W C R 8 W C R 7 Wiper Position (Sent by Master on SI) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS W Rising C Edge R 0
0
1
0
1
0
0 A0
1
0
1
0
0
0
0
0
Read Data Register (DR)
Device Type Identifier CS Falling Edge Device Addresses R/ W = 1 Instruction Opcode Register Addresses Wiper Position (Sent by X9110 on SO) W C XXXXXXR 9 W C R 8 W C R 7 Wiper Position (sent by X9110 on SO) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS W Rising C Edge R 0
0
1
0
1
0
0
A0
1
0
1
0 RB RA 0
0
8
FN8158.2 October 7, 2005
X9110 Write Data Register (DR)
Device Type Identifier CS Falling Edge 0 Device Addresses R/ W = 0 Instruction Opcode Register Address Wiper Position or Data (Sent by Master on SI) W 0XXXXXXC R 9 W C R 8 W C R 7 Wiper Position or Data (Sent by Master on SI) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS W Rising Edge C R 0
1
0
1
0
0 A0
1 1 0 0 RB RA 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS Falling Edge Device Type Identifier 0 1 0 1 0 Device Addresses 0 A0 R/ W = 1 1 Instruction Opcode 1 0 Register Address 0 RB RA 0 0 CS Rising Edge
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type Identifier CS Falling Edge 0 1 0 1 0 Device Addresses 0 A0 R/ W = 0 1 Instruction Opcode 1 1 0 RB Register Address RA 0 0 CS Rising Edge
HIGH-VOLTAGE WRITE CYCLE
Read Status Register (SR)
Device Type Identifier CS Falling Edge 0 1 0 1 0 Device Addresses 0 A0 R/ W = 1 0 Instruction Opcode 1 0 X Register Addresses 0 0 0 1 X Status Data (Sent by Slave on SO) X X X X X X X 0 Status Data (Sent by Slave on SO) 0 0 0 0 0 0 WIP CS Rising Edge
NOTES: 1. "A0": stands for the device address sent by the master. 2. WCRx refers to wiper position data in the Wiper Counter Register 3. "X": Don't Care.
9
FN8158.2 October 7, 2005
HIGH-VOLTAGE WRITE CYCLE
X9110
Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on SCK any address input with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage on V+ (referenced to VSS) (Note 4) . . . . . . . . . . . . . . . .10V Voltage on V- (referenced to VSS) (Note 4) . . . . . . . . . . . . . . . . -10V (V+) - (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Any Voltage on RH/RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ Any Voltage on RL/RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300C IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA
Recommended Operating Conditions
Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VCC) Limits (Note 4) X9110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% X9110-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
SYMBOL RTOTAL
Over recommended industrial (2.7V) operation conditions unless otherwise stated.
PARAMETER End to End Resistance End to End Resistance Tolerance Power Rating 25C, each pot
TEST CONDITIONS
MIN
TYP 100
MAX
UNITS k
20 50 3 Wiper Current = 3mA, VCC = 3V IW = 3mA, VCC = 5V X9110 (Note4) X9110-2.7 (Note 4) +4.5 +2.7 -5.5 -5.5 V-120 0.1 Rw(n)(actual) - Rw(n)(expected), where n = 8 to 1006 Rw(n)(actual) - Rw(n)(expected) (Note 5) 1 1.5 0.5 1 300 20 See Macro model 10/10/25 150 500 100 +5.5 +5.5 -4.5 -2.7 V+
% mW mA V
IW RW RW Vv+
Wiper Current Wiper Resistance Wiper Resistance Voltage on V+ pin
Vv-
Voltage on V- pin
X9110 (Note 4) X9110-2.7 (Note4)
V
VTERM
Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (Note 1)
VSS = 0V Ref: 1V
V dBV % MI (Note 3) MI (Note 3) MI (Note 3) MI (Note 3) ppm/C ppm/C pF
Relative Linearity (Note 2)
Rw(m + 1) - [Rw(m) + MI], where m = 8 to 1006 Rw(m + 1) - [Rw(m) + MI] (Note 5)
Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient CH/CL/CW NOTES: Potentiometer Capacitancies
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = RTOT / 1023 or (RH - RL) / 1023, single pot 4. VCC, V+, V- must reach their final values within 1 msec of each other. 5. n = 0, 1, 2, ...,1023; m =0, 1, 2, ..., 1022.
10
FN8158.2 October 7, 2005
X9110
D.C. Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 ICC2 ISB ILI ILO VIH VIL VOL VOH VOH PARAMETER VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage IOL = 3mA IOH = -1mA, VCC +3V IOH = -0.4mA, VCC +3V VCC - 0.8 VCC - 0.4 TEST CONDITIONS fSCK = 2.5 MHz, SO = Open, VCC = 5.5V Other Inputs = VSS fSCK = 2.5MHz, SO = Open, VCC = 5.5V Other Inputs = VSS SCK = SI = VSS, Addr. = VSS, CS = VCC = 5.5V VIN = VSS to VCC VOUT = VSS to VCC VCC x 0.7 -1 1 MIN TYP MAX 400 5 3 10 10 VCC + 1 VCC x 0.3 0.4 UNITS A mA A A A V V V V V
Endurance and Data Retention
PARAMETER Minimum Endurance Data Retention MIN 100,000 100 UNITS Data changes per bit per register years
Capacitance
SYMBOL CIN/OUT (Notes 4,6) COUT (Note 6) CIN (Note 6) TEST Input/Output capacitance (SI) Output capacitance (SO) Input capacitance (A0, CS, WP, HOLD, and SCK) TEST CONDITIONS VOUT = 0V VOUT = 0V VIN = 0V MAX 8 8 6 UNITS pF pF pF
Power-up Timing
SYMBOL tr VCC (Note 6) tPUR (Note7) tPUW (Note 7) NOTES: 6. This parameter is not 100% tested 7. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are not 100% tested. 8. ESD Rating on RH, RL, RW pins is 1.5kV (HBM, 1.0A leakage maximum), ESD rating on all other pins is 2.0kV. PARAMETER VCC Power-up Rate Power-up to Initiation of read operation Power-up to Initiation of write operation MIN 0.2 MAX 50 1 50 UNITS V/ms ms ms
A.C. Test Conditions Input pulse levels
Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
11
FN8158.2 October 7, 2005
X9110 Equivalent A.C. Load Circuit
5V 1462 SO pin 2714 100pF SO pin 1217 100pF 2.7V 1382 RH CL 10pF CW 25pF RW CL 10pF SPICE Macromodel RTOTAL
RL
AC Timing
SYMBOL fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SSI/SPI clock frequency SSI/SPI clock cycle time SSI/SPI clock high time SSI/SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs CS deselect time WP, A0 setup time WP, A0 hold time 100 0 0 400 50 50 100 100 20 0 50 50 0 400 150 150 150 150 50 50 50 50 500 100 PARAMETER MIN MAX 2.0 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
12
FN8158.2 October 7, 2005
X9110
High-Voltage Write Cycle Timing
SYMBOL tWR PARAMETER High-voltage write cycle time (store instructions) TYP. 5 MAX. 10 UNITS ms
XDCP Timing
SYMBOL tWRPO tWRL PARAMETER Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) MIN. 5 5 MAX. 10 10 UNITS s s
Symbol Table
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
13
FN8158.2 October 7, 2005
X9110 Timing Diagrams
Input Timing
tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC ... tWH ... tLAG
tFI LSB
tRI
SO
High Impedance
Output Timing
CS
SCK tV SO MSB tHO
... tDIS ... LSB
SI
ADDR
Hold Timing
CS tHSU SCK tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH ...
14
FN8158.2 October 7, 2005
X9110
XDCP Timing (For All Load Instructions)
CS
SCK
... tWRL MSB ... LSB
SI
RW
SO
High Impedance
Write Protect And Device Address Pins Timing
CS tWPASU WP A0 A1
(Any Instruction) tWPAH
Applications information
Basic Configurations Of Electronic Potentiometers
VR +VR
RW
I
Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current
15
FN8158.2 October 7, 2005
X9110
Application Circuits
Noninverting Amplifier Voltage Regulator
VS
+ - VO VIN 317 R1 VO (REG)
R2 R1
Iadj R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
Comparator with Hysterisis
R1 VS 100k - +
R2
VS
- + VO
VO } } TL072 R1 R2
10k 10k +12V -12V 10k
VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min)
16
FN8158.2 October 7, 2005
X9110
Application Circuits (continued)
Attenuator C VS R1 - VS R3 R4 R1 = R2 = R3 = R4 = 10kW R1 + VO R2 R + - VO Filter
R2
VO = G VS -1/2 G +1/2
Inverting Amplifier R1 } VS R2 }
GO = 1 + R2/R1 fc = 1/(2RC)
Equivalent L-R Circuit
- + VO
C1 VS
R2 + - R1 R3
VO = G VS G = - R2/R1
ZIN
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2
Function Generator C
- + } RA } RB
R2
R1 - +
frequency R1, R2, C amplitude RA, RB
17
FN8158.2 October 7, 2005
X9110 Packaging Information
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN8158.2 October 7, 2005

▲Up To Search▲

Price & Availability of X9110TV14

	To Download X9110TV14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .